-- Student name: Uyen Nguyen, Joseph Hamann
-- Student ID number: 24701971, 37563702

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity lab2_tb is
end lab2_tb;

architecture lab2_tb_arch of lab2_tb is
-- component declaration	
component lab2
	 port(
          clk     : in  STD_LOGIC;
          reset_N : in  STD_LOGIC;
          count   : out STD_LOGIC_VECTOR(2 downto 0)
       );
	end component;
	
-- component specification
for all: lab2 use entity work.lab2(lab2_arch);

-- signal declaration
signal  clock : STD_LOGIC := '1';
signal reset_N : STD_LOGIC := '1';
signal Z : STD_LOGIC_VECTOR(2 downto 0);
signal expected_Z	: STD_LOGIC_VECTOR (2 downto 0) := "000";

begin
clock <= (not clock) after 5ns;
reset_N <= '0' after 175ns, '1' after 185ns, '0' after 205ns, '1' after 215ns, '0' after 245ns,
 '1' after 255ns, '0' after 295ns, '1' after 305ns, '0' after 355ns, '1' after 365ns, '0' after 425ns, '1' after 435ns;
--run sequence twice and then reset in the middle of each value
--expected sequence: 0,5,2,7,4,1,6,3,0,5,0,5,2,0,5,2,7,0,5,2,7,4,0,5,2,7,4,1,0,5,2,7,4,1,6,0,5,2,7,4,1,6,3,0

	expected_Z <= "101" after 10 ns, "010" after 20 ns, "111" after 30 ns,
	 "100" after 40 ns, "001" after 50 ns, "110" after 60 ns, "011" after 70 ns,
	  "000" after 80 ns, "101" after 90 ns, "010" after 100 ns,
	   "111" after 110 ns, "100" after 120 ns, "001" after 130 ns, "110" after 140 ns,
	    "011" after 150 ns, "000" after 160 ns, "101" after 170 ns, "000" after 175 ns, 
	    "101" after 190 ns, "010" after 200 ns, "000" after 205 ns, "101" after 220 ns,
	    "010" after 230 ns,"111" after 240 ns,"000" after 245 ns,"101" after 260 ns,
	    "010" after 270 ns,"111" after 280 ns,"100" after 290 ns,"000" after 295 ns,"101" after 310 ns,
	    "010" after 320 ns,"111" after 330 ns,"100" after 340 ns,"001" after 350 ns,"000" after 355 ns,"101" after 370 ns,
	    "010" after 380 ns,"111" after 390 ns,"100" after 400 ns,"001" after 410 ns,"110" after 420 ns,"000" after 425 ns,
	    "101" after 440 ns,"010" after 450 ns,"111" after 460 ns,"100" after 470 ns,"001" after 480 ns,"110" after 490 ns,
	    "011" after 500 ns,"000" after 510 ns;

C1: lab2 port map(clock, reset_N, Z);
  
process
begin	
	wait for 3 ns;
 	assert Z = expected_Z report "Z not equal to expected_Z" severity ERROR;
 	wait for 2 ns;
end process;
end lab2_tb_arch;

